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Home >Departments >Electronics and Communication Engineering >Faculty

Dr. Alak Majumder, Senior Member IEEE

Assistant Professor, Electronics and Communication Engineering

Research Areas:

VLSI Circuit, Power Supply Noise, Clock Gating, Wireline Communication, Optical Logic

 alak@nitap.ac.in
 +91-9436288578
Address:

Google Scholar, Personal Website

Workshp/Conference Attended

1. Electronic Systems: Devices, IC and Applications

Institute : NIT Arunachal Pradesh
Date : 14 - 18 March 2022
Type: National
Place : Jote
Organised by Dr. Alak Majumder

2. Electrochemical nano-bio sensing and bio/CMOS interfaces

Institute : EPFL Switzerland
Date : 15 - 19 June 2020
Type: International
Place : Online
Attended by Dr. Alak Majumder

3. Quantum Computing: A Paradigm Shift

Institute : APC College, New Barrackpur, Kolkata
Date : 29 - 30 June 2020
Type: International
Place : Online
Attended by Dr. Alak Majumder

4. International Conference on Electronic System and Intelligent Computing (ESIC - 2020)

Institute : NIT Arunachal Pradesh
Date : 02 - 04 March 2020
Type: International
Place : Itanagar, Arunachal Pradesh
Organised by Dr. Alak Majumder and Dr. Preetisudha Meher

5. Phase Locked Loop

Institute : IIT Madras
Date : 17 - 22 December 2018
Type: National
Place : IIT Madras
Attended by Dr. Alak Majumder

6. Tape out Flow of ASIC

Institute : NIT Arunachal Pradesh
Date : 25 - 30 June 2018
Type: National
Place : Yupia
Organised by Dr. Alak Majumder

7. Design Flow on Xilinx VIVADO

Institute : NIT Arunachal Pradesh
Date : 30 Sept - 1st Oct 2016
Type: National
Place : Yupia
Organised by Dr. Alak Majumder

8. VLSI Design Flow using Xilinx VIVADO Targeting Xilinx 7-series FPGA and Zynq SOC Architecture

Institute : Core-EL Technologies
Date : 06 - 10 September 2016
Type: National
Place : Bangalore
Attended by Dr. Alak Majumder

9. Recent Trends in VLSI Design

Institute : NIT Arunachal Pradesh
Date : 16 - 22 September 2015
Type: National
Place : Yupia
Organised by Dr. Alak Majumder

10. Research Challenges on Quantum & Reversible Computing

Institute : NIT Meghalaya
Date : 19-20 March 2015
Type: National
Place : Shillong
Attended by Dr. Alak Majumder

11. Schematic & Layout design in CADENCE’

Institute : NIT Meghalaya
Date : January 2014
Type: National
Place : Shillong
Attended by Dr. Alak Majumder

Alak Majumder, Senior Member IEEE