2024

1. Kuntal Chakraborty, Alak Majumder and Abir J Mondal "Time Domain and Area Efficient Smart Temperature Sensor Exploiting Channel Length Modulation Coefficient", World Scientific Journal of Circuits, Systems and Computers, vol. 33 , issue 13, 2024. (10.1142/S0218126624502384)[SCI/SCIE, Q3]

2. Kuntal Chakraborty and Abir J Mondal "On-chip oscillator based temperature-to-digital converter Exploiting channel length modulation coefficient λ", Elsevier Integration the VLSI Journal, vol. 96, 2024. (10.1016/j.vlsi.2024.102168)[SCI/SCIE, Q3]

3. Kuntal Chakraborty and Abir J Mondal "Programmable Delay Cell based Area Efficient Time-Mode Smart Temperature Sensor Exploiting Channel Length Modulation Coefficient λ", Elsevier Sensors and Actuators A: Physical, vol. 377 , issue 115708, 2024. (https://doi.org/10.1016/j.sna.2024.115708)[SCI/SCIE, Q1]

4. Kuntal Chakraborty and Abir J Mondal "A 17pJ- External Oscillator Less Differential Delay Cell Based Time-Domain Smart Temperature Sensor", World Scientific Journal of Circuits, Systems and Computers, , 2024. (10.1142/S0218126625500513)[SCI/SCIE, Q3]

2023

1. Mithilesh Kumar and Abir J Mondal "An Improved Latch for SerDes Interface: Design and Analysis under PVT and AC Noise", Radioengineering, vol. 32 , issue 2, pp. 207-220, 2023. (10.13164/re.2023.0197)[SCI/SCIE, Q3]

2022

1. Mithilesh Kumar and Abir J Mondal "A New Low Power Current Steering Logic Circuit for the Design of Digital Subsystem", Taylor & Francis International Journal of Electronics, vol. 109 , issue 3, pp. 497-519, 2022. (10.1080/00207217.2021.1914188)[SCI/SCIE, Q3]

2. Mithilesh Kumar, Alak Majumder and Abir J Mondal "Simulation and Analysis of a Digitally Controlled Differential Delay Circuit Under Process, Voltage, Temperature and Noise due to Injection of High Current", World Scientific Journal of Circuits, Systems and Computers, vol. 31 , issue 16, 2022. (10.1142/S0218126622502760)[SCI/SCIE, Q3]

3. Mithilesh Kumar, Alak Majumder, Abir J Mondal, Arijit Raychowdhury and Bidyut K Bhattacharyya " A Low Power and PVT Variation Tolerant Mux-Latch for Serializer Interface and on-chip Serial Link", Elsevier Integration the VLSI Journal, vol. 87, pp. 364-377, 2022. (10.1016/j.vlsi.2022.08.008)[SCI/SCIE, Q3]

4. Mithilesh Kumar and Abir J Mondal "A PVT Tolerant Latch in a 90-nm CMOS and Performances Under AC Noise", Taylor & Francis International Journal of Electronics, vol. 111 , issue 1, pp. 86-104, 2022. (10.1080/00207217.2022.2148287)[SCI/SCIE, Q3]

2021

1. Anirban Tarafdar, Abir J Mondal, U Bera and B K Bhattacharyya "A PVT Aware Differential Delay Circuit and its Performance Variation due to Power Supply Noise ", Elsevier Integration the VLSI Journal, vol. 76, pp. 159-171, 2021. (10.1016/j.vlsi.2020.10.004)[SCI/SCIE, Q3]

2020

1. Abir J Mondal, Paromita Bhattcharjee, Pinaki Chakraborty and Bidyut K Bhattacharyya, "MOS Amplifier Design Methodology for Optimum Performance", Taylor & Francis – IET Journal of Research, vol. 66 , issue 4, pp. 478-490, 2020. (10.1080/03772063.2018.1506267)[SCI/SCIE, Q3]

2. Abir J Mondal, J Talukdar and Bidyut K Bhattacharyya, "Variation Aware Design of Voltage Controlled Swing Ring Oscillator", Taylor & Francis – International Journal of Electronics, vol. 107 , issue 1, pp. 99-124, 2020. (10.1080/03772063.2018.1506267)[SCI/SCIE, Q3]

3. Madhusudan Maity, Suraj Kumar Saw, Abir J Mondal and Alak Majumder, "A Hybrid Design Approach of PVT Tolerant, Power Efficient Ring VCO", Elsevier Ain Shams Engineering Journal, vol. 11 , issue 2, pp. 265-272, 2020. (10.1016/j.asej.2019.10.009)[SCI/SCIE, Q3]

4. Abir J Mondal, J Talukdar and Bidyut K Bhattacharyya, "Estimation of Frequency and Amplitude of Ring Oscillator Built Using Current Sources", Elsevier Ain Shams Engineering Journal, vol. 11 , issue 3, pp. 677-686, 2020. (10.1016/j.asej.2020.01.006)[SCI/SCIE, Q3]

2019

1. Alak Majumder, M Das, Suraj K Saw, Abir J Mondal and Bidyut K Bhattacharyya, "Variation Aware Design of 50-Gbit/s, 5.027-fJ/bit Serializer Using Latency Combined Mux-Dual Latch for Inter-Chip Communication", IEEE Trans. on Circuits and Systems I (TCAS I), vol. 66 , issue 3, pp. ---, 2019. (10.1109/TCSI.2018.2877571)[SCI/SCIE, Q1]

2. Suraj Kumar Saw, Sandeep Kumar Yadav, Madhusudan Maity, Abir J Mondal and Alak Majumder, "A Design Approach of Higher Oscillation VCO made of CS Amplifier with Varying Active Load", Springer – Microsystem Technologies, vol. 24 , issue 2, 2019. (10.1007/s00542-019-04500-5)[SCI/SCIE, Q2]

2018

1. Paromita Bhattcharjee, Abir J Mondal and Alak Majumder, "A Graphical Approach to Design and Optimization of MOS Amplifier", Journal of Engineering Science & Technology, vol. 13 , issue 1, pp. 265-279, 2018.[SCI/SCIE, Q3]

2017

1. Abir J Mondal, Alak Majumder, Bidyut K Bhattacharyya and Pinaki Chakraborty, "A Process Aware Delay Circuit with Reduce Impact of Input Switching at GHz Frequencies", IEEE VLSI Circuits and Systems Letter, vol. 3 , issue 2, pp. 6-12, 2017.[Scopus, Others]

2. Alak Majumder, Abir J Mondal and Bidyut K Bhattacharyya, "A 65-nm Design of 0.6 V/8.98 uW PVT Aware Dynamic Analog Comparator for High Speed Data Reconstruction Applications", Journal of Low Power Electronics (JOLPE), vol. 13 , issue 3, pp. 1-9, 2017. (10.1166/jolpe.2017.1496)[SCI/SCIE, Q3]

3. B. Nath, Alak Majumder, M Das, Abir J Mondal, Pinaki Chakraborty and Bidyut Kumar Bhattacharyya, "Voltage Keeper Based 28.27 µW New Frequency Divider Circuit in 90 nm Technology for Gigascale SerDes Application", IEEE VLSI Circuits and Systems Letter, vol. 3 , issue 2, pp. 13-17, 2017.[Scopus, Others]

2016

1. Alak Majumder, Abir J Mondal and Bidyut K Bhattacharyya, "Threshold Adjustment of Receiver Chip to Achieve a Data Rate >66 Gbit/sec in Point to Point Interconnect", Elsevier Integration the VLSI Journal, vol. 58, pp. 356-368, 2016. (10.1016/j.vlsi.2016.11.004)[SCI/SCIE, Q3]

2. Abir J Mondal, Alak Majumder and Bidyut K Bhattacharyya, "A Mathematical Formulation to Design and Implementation of a Low Voltage Swing Transceiver Circuit", Elsevier Integration the VLSI Journal, vol. 58, pp. 356-368, 2016. (10.1016/j.vlsi.2016.11.013)[SCI/SCIE, Q3]

2015

1. P L Singh, A Majumder, B Chowdhury, A J Mondal, T S Shekhawat, "Reducing Delay & Quantum Cost in the Novel Design of Reversible Memory Elements", ELSEVIER 3rd International Conference on Recent Trends in Computing (ICRTC), Procedia Computer Science, vol. 57, pp. 189-198, 2015. (10.1016/j.procs.2015.07.423)[Scopus, Others]

2. A Majumder, P L Singh, B Chowdhury and A J Mondal, "Efficient Design & Analysis of N-bit Reversible Shift Registers", ELSEVIER 3rd International Conference on Recent Trends in Computing (ICRTC), Procedia Computer Science, vol. 57, pp. 199-208, 2015. (10.1016/j.procs.2015.07.431)[Scopus, Others]

3. Sandeep Kr Singh, Abir J Mondal and Alak Majumder, "Generation and Performance Evaluation of Reconfigurable Fault Tolerant Routing Algorithm for 2D-Mesh NoC", ELSEVIER 3rd International Conference on Recent Trends in Computing (ICRTC), Procedia Computer Science, vol. 57 , issue -, pp. 232-240, 2015. (10.1016/j.procs.2015.07.471)[Scopus, Others]

2012

1. Ashis Kumar Mal, Abirjyoti Mondal, Om Prakash Hari and Rishi Todani, "Simulator Based Simplified Design Approach of a CMOS 2 Stage Opamp", IACSIT, vol. 4 , issue 6, pp. 826-830, 2012.